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Integrated Circuit Systems, Inc.
ICS9169C-41
Frequency Generator for PentiumProTM Based Systems
General Description
The ICS9169C-41 is a Clock Synthesize/Driver chip for Pentium, PentiumPro or Cyrix 68x86 based motherboards using SDRAM. Features include four dual purpose I/O pins which provide extra CPU clocks and enable the part to be packaged in a low-cost 34-pin SSOP package. These four pins latch the select inputs at the internal Power-On Reset. Additionally, the device meets the Pentium and PentiumPro power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. The ICS9169C-41 clock outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits and innovative circuit layout techniques enable the ICS9169C-41 to have lower EMI than other clock devices. The ICS9169C-41 accepts a 14.318MHz reference crystal or clock as its input and runs from a 3.3V supply.
Features
* * * * * * * * * * * * 12 selectable CPU/SDRAM/AGP clocks up to 75 MHz Six PCI clocks, synchronous or asynchronous mode, pin selectable by Bus Select input (pin 19) One USB clock at 48MHz, meets Intel jitter, accuracy, as well as rise and fall time requirements One I/O clock at 24MHz Two Ref. Clocks at 14.318MHz CPU clocks to PCI clock skew of 1-4ns (CPU early) Low CPU and PCI clock jitter <200ps Low skew outputs, skew window 250ps for CPU clocks and for PCI clocks Improved output drivers are designed for low EMI Test Mode 3.3V 10% operation Space saving and low cost 34-pin SSOP package
Block Diagram
Pin Configuration
34-Pin SSOP
Pentium is a trademark on Intel Corporation.
9169-41Rev D 5/02/00
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9169C-41
Pin Descriptions
PIN NUMBER 1, 8, 14, 26 2 3 4, 11 20, 23, 29 PIN NAME VDD X1 X2 GND CPUCLK1 5 FS2 18, 17, 13, 12, 10, 9, 7, 6, CPUCLK(11,10,7:2) CPUCLK8 15 FS1 CPUCLK9 16 FS0 CPUCLK12 19 BSEL 28, 27, 25, 24, 22, 21 30 31 32 33 34 PCICLK (6:1) USBCLK IOCLK AVDD REF1 REF0 IN OUT OUT OUT PWR OUT OUT IN OUT IN OUT IN OUT OUT TYPE PWR IN OUT PWR OUT DESCRIPTION Voltage Supply Crystal input. Nominally 14.318MHz Crystal output. Nominally 14.318MHz Ground Processor clock output which are a multiple of the input reference clock as shown in the preceding table. Frequency multiplier select pins. See shared pin programming description later in this data sheet for further explanation. CPU clock output Processor clock output which are a multiple of the input reference clock as shown in the preceding table. Frequency multiplier select pin. See shared pin programming description later in this data sheet for further explanation. Processor clock output which are a multiple of the input reference clock as shown in the preceding table. Frequency multiplier select pins. See shared pin programming description later in this data sheet for further explanation. Processor clock output which are a multiple of the input reference clock as shown in the preceding table. Selection for synchronous (High) or asynchronous (Low) bus clock operation. See shared pin programming description later in this data sheet for further explanation. PCI Clock outputs. syncronous to CPU with 1-4ns delay. USB clock output 48 MHz I/O clock output 24 MHz Analog Voltage Supply Reference clock output (14.318 MHz) Reference clock output (14.318 MHz) for ISA slots (drives CLOAD = 45pF)
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ICS9169C-41
Functionality
3.3V10%, 0-70C Crystal (X1, X2) = 14.31818 MHz
FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 XTALIN 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz 14.318MHz TCLK(1) CPUCLK 33.33MHz 75.0MHz 55.0MHz HI-Z 50.0MHz 66.67MHz 60.0MHz TCLK/2(2) PCICLK(1-5) BSEL = 1 16.67MHz 37.5MHz 27.5MHz HI-Z 25.0MHz 33.33MHz 30.0MHz TCLK/4 PCICLK(1-5) BSEL = 0 32MHz 32MHz 32MHz HI-Z 32MHz 32MHz 32MHz TCLK/3 REF(0-1) 14.318MHz 14.318MHz 14.318MHz HI-Z 14.318MHz 14.318MHz 14.318MHz TCLK USBCLK 48MHz 48MHz 48MHz HI-Z 48MHz 48MHz 48MHz TCLK/2 IOCLK 24MHz 24MHz 24MHz HI-Z 24MHz 24MHz 24MHz TCLK/4
Notes 1. TCLK is supplied on XTALIN pin 2. Bidirectional CPUCLK I/O pins are high in test mode.
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ICS9169C-41
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated
DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current1 Output Low Current1 Output High Current1 Output Low Voltage1 Output High Voltage1 Output Low Voltage1 Output High Voltage1 Supply Current SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD VIN=0V VIN=VDD VOL=0.8V; for CPU, PCI, REF CLKS VOL=2.0V; for CPU, PCI, REF CLKS VOL=0.8V; for Fixed CLK VOL=2.0V; for Fixed CLK IOL=8mA; for CPU, PCI, REF IOH=-8mA; for CPU, PCI, REF IOL=18mA; Fixed CLK's IOH=-18mA; Fixed CLK's @66.6 MHz; all outputs unloaded TEST CONDITIONS MIN 0.7VDD -28.0 -5.0 16.0 19.0 2.4 2.4 TYP -10.5 25.0 -30.0 30.0 -38.0 0.3 2.8 0.3 2.8 75 MAX 0.2VDD 5.0 -14.0 -16.0 0.4 0.4 95 UNITS V V A A mA mA mA mA V V V V mA
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9169C-41
Electrical Characteristics at 3.3V
VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated
AC Characteristics PARAMETER Rise Time Fall Time Rise Time
1 1 1
SYMBOL Tr1 Tf1 Tr2 Tf2 Tr3 Tf3
TEST CONDITIONS 20pF load, 0.8 to 2.0V; All Except Ref 20pF load, 2.0 to 0.8V; All Except Ref 30pF load, 0.8 - 2.0V All Except Ref 30pF load, 2.0 - 0.8V All Except Ref 45pF; 0.8 - 2.0V; Ref only 45pF; 2.0 - 0.8V; Ref only 20, 30, 45pF load @ VOUT=1.5V CPU & PCI Clocks CPU & PCI Clocks (@ 60 & 66MHz) Ref & Fixed CLKs Ref & Fixed CLKs CPU Outputs Fixed Clocks & REF0 Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to <1% settling CPU to CPU & PCI - PCI; Same Load; @1.5V CPU(20pF) - PCI (30pF); @1.5V (CPU is Early)
MIN 45 -250 12.0 1.0
TYP 0.9 0.8 1.3 1.3 1.7 1.0 50 50 1 1.0 290 4.5 14.318 5 18 1.9 2.0 188 1.2
MAX 1.2 1.2 1.6 1.6 2.0 2.0 55 150 250 3 2.5 350 6 16.0 2.0 4.0 300 4.0
UNITS ns ns ns ns ns ns % ps ps % % ps % MHz pF pF ms ms ps ns
Fall Time1 Rise Time Fall Time Duty Cycle
1 1
Dt Tj1s1 Tjab1
1 1
Jitter, One Sigma Jitter, Absolute Jitter, Absolute
Jitter, One Sigma
1
Tj1s2 Tjab2 Tcc Fi CIN CINX ton ts Tsk1 Tsk2
Jitter - Cycle to Cycle Input Frequency1 Logic Input Capacitance1 Crystal Oscillator Capacitance1 Power-on Time1 Frequency Settling Time1 Clock Skew1 (window) Clock Skew1 (window)
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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ICS9169C-41
Technical Pin Function Descriptions
VDD This is the power supply to the internal logic of the device as well as the following clock output buffers: This pin may be operated at any voltage between 3.0 and 3.7 volts. Clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. For the actual guaranteed high and low voltage levels of these clocks, please consult the AC parameter table in this data sheet. GND This is the power supply ground return pin. X1 This pin serves one of two functions. When the device is used with a crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. X2 This pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete crystal. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. CPU (1:12) These pins are the clock output that drive the processor and other CPU related circuitry that require clocks which are in tight skew tolerance with the CPU clock. See the Functionality table at the beginning of this data sheet for a list of the specific frequencies that these clocks operate at and the selection codes that are necessary to produce these frequencies. Some of these pin serve dual functions. PCICLK Clock output driver for the PCI Bus. FS0, FS1, FS2 These pins control the frequency of the clocks at the CPU, BUS and SDRAM pins. See the Funtionality table at the beginning of this data sheet for a list of the specific frequencies that these clock operate at and the selection codes that are necessary to produce these frequencies. The device reads these pins at power-up and stores the programmed selection code in an internal data latch. If a "1" value is desired for a specific frequency selection bit,a 10K ohm resistor must be connected from the appropriate FS pin to the VDD supply. If a "O" value is desired, then the 10K resistor must be connected to ground. After the internal power On reset latches the input data, these pins become output clocks and no further frequency selection is possible. 48MHz This is a fixed frequency clock that is typically used to drive USB peripheral device needs. 24MHz This is a fixed frequency clock that is typically used to drive super I/O peripheral device needs. REF (0:1) This is a fixed frequency clock that runs at the same frequency as the input freerence clock (typically 14.31818 MHz) is and typically used to drive Video and ISA BUS requirements.
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ICS9169C-41
Ordering Information
ICS9169CF-41
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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